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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
The XGMII supports Double Data Rate (DDR) transmission, i.e. the data and control input signals are sampled on
both the rising and falling edges of the corresponding clock. The XGXS XGMII input (tx) data is sampled based on
an input clock typically sourced from the MAC or PHY device running at 156.25MHz, 1/64th of the 10Gb data rate.
The XGXS XGMII output (rx) data is referenced to a forwarded clock that is phase locked to a 156.25MHz (typical)
input reference.
The control signal for each lane is de-asserted when a data octet is being sent on the corresponding lane and
asserted when a control character is being sent. Supported control octet encodings are shown in Table 2. All data
and control signals are passed directly to/from the 8b/10b encoding/decoding blocks with no further processing by
the XGMII block. Note that the packet Start control word is only valid on lane 0.
Table 2. XGMII Control Encoding
Control
0
1
1
1
1
1
1
1
1
1
1
Data
0x00 - 0xFF
0x00 - 0x06
0x07
0x08 - 0x9B
0x9C
0x9D - 0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
Description
Normal data transmission
Reserved
Idle
Reserved
Sequence (only valid on lane 0)
Reserved
Start (only valid on lane 0)
Reserved
Terminate
Error
Reserved
The XGMII blocks incorporate slip buffers that accommodate small differences between XGMII and XAUI timing by
inserting or deleting idle characters. The slip buffer is implemented as a 256 x 72 FIFO. There are four ? ags out of
the FIFO: full, empty, partially full and partially empty. The partially empty ? ag is used as the watermark to start
reading from the FIFO. If the difference between write and read pointers falls below the partially empty watermark
and the entire packet has been transmitted, idle characters are inserted until the partially full watermark is reached.
No idle is inserted during data transmission.
XAUI-to-XGMII Translation (Receive Interface)
A block diagram of the XGXS receive data path was shown previously in Figure 3. The XGXS solution utilizes
ORT82G5 SERDES Quad B. The receive interface converts the incoming XAUI stream into XGMII-compatible sig-
nals. At the ORT82G5 embedded core interface, the XGXS receive block receives 40 bits of data at 78MHz (32 bits
of data, four bits of control and four unused bits) from each XAUI lane. Data from the embedded core are ? rst
passed to the RX rate converter block where the 144 bits of data and control received at a 78MHz rate are con-
verted to 72 bits of data and control clocked at 156MHz.
The data from the RX rate converter is passed to the RX decoder. The RX decoder block converts the XAUI code
to the XGMII code. Table 3 shows the 8b/10b code points. Table 4 shows the code mapping between the two
domains in the receive direction. XAUI /A/, /R/, /K/ characters are translated into XGMII Idle (/I/) characters.
Data from the RX decoder block is written to the RX slip buffer. As mentioned previously, the slip buffers are
required to compensate for differences in the write and read clocks derived from the XAUI and XGMII reference
clocks, respectively. Clock compensation is achieved by deleting (not writing) idle cells into the buffer when the
“almost full” threshold is reached and by inserting (writing) additional idle cells into the buffer when the “almost
empty” threshold is reached. All idle insertion/deletion occurs during the Inter-Packet Gap (IPG) between data
frames.
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